SKU : AVR JTAG ICE.
AVR JTAG is with Atmel company AVR Studio + iccavr or WINAVR phase with a complete set of JTAG interface based on the chip debugging tools, support for all the AVR eight RISC instruction with JTAG mouth microprocessor. JTAG interface is a 4 line conform to the IEEE 1149.1 standard test access port (TAP) controller. IEEE standard provides a effective circuit board connectivity test standard method (boundary scan). The Atmel AVR devices have expanded the support completely programming and chip debug function. AVR JTAG simulation device is used for chip hardware simulation, such as program single step, set breakpoints, etc., through the hardware simulation can understand chip inside the detailed operation procedures. AVR JTAG emulator used for chip simulation operation, at the same time can also through the JTAG interface for chip programming (will program write chip).
- With a 0.5A PTC FUSE
- Wide operating voltage, support 3.3V
- Latest version of design, with a buffer chip (to prevent improper operation impact firmware)
- This simulation software is compatible upwards and downwards, Software Support AVR ATUDIO latest version 4.12/4.14/4.16/4.17/4.18